Voltage gain amplifier for converting a single input to a differential output

ABSTRACT

The present invention relates to a voltage gain amplifier for converting a single analog input to a differential output and controlling a voltage gain, comprising a single input charging/discharging part, a differential output operational amplifier, a first and second input voltage transferring part, a first and second voltage holding part and a frequency compensating part, and therefore, making it possible to generate a differential input signal, which is used as an input to an ADC(Analog-to-Digital Converter) of an audio CODEC(Coder/Decoder), by using a fully-differential output operational amplifier whose output is transmitted as a differential output. Also, the present invention gives an advantage of making the chip size smaller than the prior art does, resulting from the fact that resistors are replaced by capacitors and switches when integrated into a chip.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a voltage gain amplifier, whichconsists of analog switches, capacitors and a fully-differentialamplifier, used for converting a single analog input to a differentialoutput and controlling a voltage gain.

2. Description of the Prior Art

An Analog-to-Digital Converter(referred to hereinafter as ADC), whichadopts an oversampling method in order to support Multimedia Audio andCoder/Decoder(referred to hereinafter as CODEC), uses a sigma-deltamodulator that receives an analog signal as an input. The sigma-deltamodulator needs a voltage gain amplifier for improving thesignal-to-noise ratio and a differential input for improving the dynamicrange and power supply rejection ratio.

FIG. 1 shows the schematic structure of a conventional voltage gainamplifier for processing an analog signal. FIG. 2 shows the structure ofa conventional programmable voltage gain amplifier. FIG. 3 shows thestructure of a conventional voltage gain amplifier for converting ananalog signal to a differential output, in which A denotes amoperational amplifier, R, R₁ to R₂.spsb.N₊₁ denote a registor and S₁ toS₂.spsb.N denote a switch, respectively.

Referring to FIG. 1, the input voltage V_(in) is inputted to aninversion input part of the operational amplifier A by way of theimpedance Z₁, output voltage V_(out) is fed back to the inversion inputpart of the operational amplifier A by way of the impedance Z₂, and thenon-inversion input part is grounded.

Supposing that impedances Z₁, Z₂ are resisstors R₁, R₂, respectively,and R₁ is smaller than R₂, a voltage gain is: ##EQU1##

That is, the output voltage is amplified by R₂ /R₁ times of the inputvoltage with an inverse polarity of the input voltage.

Referring to FIG. 2, signals S₁ ˜S₂.spsb.N decoded by the N-bit decoderare used for selecting the switches of the voltage gain amplifier inorder to output the desired voltage gain.

However, as this kind of a voltage gain amplifier can not be used as adifferential input for a sigma-delta modulator, an inversion amplifierwith a voltage gain of 1 is further required, as shown in FIG. 3.Therefore, the prior art has the drawbacks of a large chip size and adifficulty in integrating resistors on the chip.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a voltage gainamplifier for converting a single input to a differential output bydischarging a charged voltage in a capacitor with an inverted polarityand a non-inverted polarity, which uses a fully-differential amplifierinstead of a single-output inversion amplifier and also uses switchesand capacitors instead of resistors, in order to improve the integrationdensity.

In accordance with one aspect of the present invention, a voltage gainamplifier for converting a single input to a differential outputincludes:

a fully-differential output operational amplifying means, which has aninversion input terminal, a non-inversion input terminal, an inversionoutput terminal and a non-inversion output terminal, for amplifying thetwo inputted signals and then outputting the two amplified signals to afirst output terminal and a second output terminal, respectively, thephase of the one output signal being opposite to the phase of the otheroutput signal;

a first single input charging/discharging means, connected to saidinversion input terminal of said fully-differential output operationalamplifying means, for charging/discharging the input voltage V_(in) ;

a second single input charging/discharging means for providing a signalwhose phase is inversed compared with the phase of the signal providedby said first single input charging/discharging means, connected to saidnon-inversion input terminal of said fully-differential outputoperational amplifying means;

a first input voltage transferring means, of which one end is connectedto said inversion input terminal of said fully-differential outputoperational amplifying means and the other end is connected to saidfirst output terminal, respectively, for transferring the input voltageby a switching operation;

a second input voltage transferring means, of which one end is connectedto said non-inversion input terminal of said fully-differential outputoperational amplifying means and the other end is connected to saidsecond output terminal, respectively, for transferring the input voltageby a switching operation; and

a frequency compensating means for outputting a first and second outputvoltage after compensating frequency such that the output signals ofsaid fully-differential output operational amplifying means can bestably operated within a given bandwidth.

BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS

FIG. 1 shows a schematic diagram of a conventional voltage gainamplifier for an analog signal;

FIG. 2 shows a schematic diagram of a conventional programmable voltagegain amplifier;

FIG. 3 shows a schematic diagram of a conventional voltage gainamplifier for converting a single input to a differential output;

FIG. 4 shows a circuit diagram of the voltage gain amplifier inaccordance with one embodiment of the present invention; and

FIG. 5 shows a circuit diagram of the voltage gain amplifier inaccordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the attached drawings, the preferred embodiment of thepresent invention will be fully explained. FIG. 4 and FIG. 5 show thecircuit diagram of the voltage gain amplifier in accordance with oneembodiment and another embodiment of the present invention, wherein 1denotes the fully-differential output operational amplifier, 2 denotesthe single input charging/discharging part, 3 and 3' denote the inputvoltage transferring part, 4 and 4' denote the voltage holding part, and5 denotes the frequency compensating part, respectively.

As shown in FIG. 4, the single input charging/discharging part 2consists of a first and second charging/discharging part which cancharge/discharge the single input voltage V_(in) by means of theswitching operation such that the phase of the output signal of saidfirst charging/discharging part is opposite to the phase of the outputsignal of said second charging/discharging part but the amplitude of thetwo output signals is equal.

The fully-differential output operational amplifier 1 amplifies theamplitude of the fully-differential mode signals tramsmitted from aninversion and non-inversion input terminal, and then outputs theamplified signals whose phase is opposite each other to a first andsecond output terminal.

The input voltage transferring part 3, 3', connected to each input andoutput terminal of said fully-differential output operational amplifier1, transfers an input voltage by a switching operation.

The voltage holding means 4, 4', connected to both ends of said inputvoltage transferring part 3, 3', decrease a high-frequency noise.

The frequency compensating part 5 outputs a first and second outputvoltage after compensating frequency such that the output signals ofsaid fully-differential output operational amplifying means can bestably operated within a given bandwidth.

Referring to FIG. 4, the first charging/discharging part of said singleinput charging/discharging part 2 includes the switch S₁₁ for switchingthe input voltage V_(in), the sampling capacitor C_(S+) of which one endis connected to said switch S₁₁, the switch S₂₁ connected between theother end of said sampling capacitor C_(S+) and the inversion inputterminal of said fully-differential output operational amplifier 1, theswitch S₂₂ connected between one end of said sampling capacitor C_(S+)and the ground, and the switch S₁₂ connected between one end of saidsampling capacitor C_(S+) and the ground.

Also, the second charging/discharging part of said single inputch7/arging/discharging part 2 includes the switch S₁₃ for switching theinput voltage V_(in), the switch S₂₃ connected between said switch S₁₃and the non-inversion input terminal of said fully-differential outputoperational amplifier 1, the sampling capacitor C_(S-) connected betweensaid switches S₁₃ and S₂₃, and switches S₁₄, S₂₄ connected in parallelbetween the sampling capacitor C_(S-) and the ground.

Said input voltage transferring part 3 consists of the switch S₂₅connected to the inversion input terminal of said fully-differentialoutput operational amplifier 1, the capacitor C_(H+) connected to saidswitch S₂₅, the switch S₂₆ connected between said capacitor C_(H+) andthe first output terminal, and the switches S₁₅, S₁₆ connected betweenboth ends of said capacitor C_(H+) and the ground.

Meanwhile, said input voltage transferring part 3' consists of theswitch S₂₇ connected to the non-inversion input terminal of saidfully-differential output operational amplifier 1, the capacitor C_(H-)connected to said switch S₂₇, the switch S₂₈ connected between saidcapacitor C_(H-) and the second output terminal, and switches S₁₇, S₁₈connected between both ends of said capacitor C_(H-) and the ground.

The voltage holding part 4 has the capacitor C_(F+) whose one end isconnected between the inversion input part of said fully-differentialoutput operational amplifier 1 and said switch S₂₅ and the other end isconnected between the first output terminal of said fully-differentialoutput operational amplifier 1 and said switch S₂₆.

Also, the voltage holding part 4' has the capacitor C_(F-) whose one endis connected between the non-inversion input part of saidfully-differential output operational amplifier 1 and said switch S₂₇and the other end is connected between the second output terminal ofsaid fully-differential output operational amplifier 1 and said switchS₂₈.

The frequency compensating part 5 includes the capacitor C_(C+)connected between the first output terminal and the ground, and thecapacitor C_(C-) connected between the second output terminal and theground.

Meanwhile, a plurality of switches S₁₁ ˜S₁₈, S₂₁ ˜S₂₈ are a transmissiongate or an NMOS transistor and have a switching operation that in casesaid switches S₁₁ ˜S₁₈ are `on`, said switches S₂₁ ˜S₂₈ are `off` bymeans of the clock which applies to the gate, and on the contrary, incase said switches S₁₁ ˜S₁₈ are `off`, said switches S₂₁ ˜S₂₈ are `on`.However, the clock frequency f_(C) is the same.

When said switches S₁₁ ˜S₁₄ of the single input charging/dischargingpart 2 become `on`, the input voltage V_(in) minus the ground voltageV_(ref) is charged in said sampling capacitors C_(S+) and C_(S-), and atthe same time, a potential difference between both ends of saidcapacitors C_(H+), C_(H-) of the input voltage transferring part 3, 3'is 0 voltage.

Meanwhile, when said switches S₁₁ ˜S₁₄ of the single inputcharging/discharging part 2 become `off` and said switches S₂₁ ˜S₂₄ ofthe single input charging/discharging part 2 become `on`, voltage V_(in)-V_(ref), which was charged in said sampling capacitors C_(S+) andC_(S-), is applied to said inversion and non-inversion input terminal ofthe fully-differential output operational amplifier 1.

At this time, the two input terminal voltages have a different electricpolarity from each other, and are discharged into said capacitors C_(H+)and C_(H-) of the input voltage transferring parts 3, 3'.

Thus, the ratio of the output voltage to the input voltage is: ##EQU2##

Thus, the output voltage is amplified in case C_(S+) is greater thanC_(H+). In the meantime, C_(H+) is equal to C_(H-), and C_(S+) is equalto C_(S-).

However, the output signal has high-frequency noises. Thesehigh-frequency noises can be eliminated by said capacitors C_(F+),C_(F-) of the voltage holding parts 4, 4' of which the cutoff-frequency,respectively, is: ##EQU3##

In the meantime, said capacitors C_(C+) and C_(C-) of the frequencycompensating part 5 enable said fully-differential output operationalamplifier 1 to operate stably within a given bandwidth.

Based on FIG. 4, FIG. 5 shows the circuit diagram of the voltage gainamplifier, wherein the voltage gain varies from 0 dB to +22.5 dB with aninterval +1.5 dB. That is, 16 different voltage gains are obtained byturning `on` and `off` switches with the help of the switch controlsignal to which the 4-bit digital signal is decoded by the decoder.

As shown in FIG. 5, said single input charging/discharging part 2 iscomposed of 4 first charging/discharging parts whose inter-connection isparallel and 4 second charging/discharging parts whose inter-connectionis also parallel. Also, said input voltage transferring parts 3, 3' havea 4-stage parallel connection, respectively.

Meanwhile, said capacitors C_(1H), C_(2H), C_(3H), C_(4H), C_(1S),C_(2S), C_(3S), and C_(4S) have the following relation:

C_(1H) =C_(2H)

C_(3H) =2 C_(1H)

C_(4H) =4 C_(1H)

C_(1S) =C_(1H) +C_(2H) +C_(3H) +C_(4H) =8 C_(1H)

C_(2S) =0.1885·C_(1S)

C_(3S) =0.22404·C_(1S)

C_(4S) =0.26626·C_(1S)

As shown in FIG. 4, the clock signal generated by decoding the 4-bitdigital signal enables each switch to become turned `on` or `off`.

For example, said switches 1S₁₁ ˜1S₁₄, 1S₂₁ ˜1S₂₄, 1S₁₅ ˜1S₁₈, 1S₂₅˜1S₂₈, 2S₁₅ ˜2S₁₈, 2S₂₅ ˜2S₂₈, 3S₁₅ ˜3S₁₈, 3S₂₅ ˜3S₂₈, 4S₁₅ ˜4S₁₈, and4S₂₅ ˜4S₂₈ become turned `on` or `off` in order to obtain a gain of 0dB. Said switches 1S₁₁ ˜1S₁₄, 1S₁₅ ˜1S₁₈, 2S₁₅ ˜2S₁₈, 3S₁₅ ˜3S₁₈, and4S₁₅ ˜4S₁₈ are operated by a clock signal whose phase is opposite to thephase of the clock signal which controls said switches 1S₂₁ ˜1S₂₄, 1S₂₅˜1S₂₈, 2S₂₅ ˜2S₂₈, 3S₂₅ ˜3S₂₈, and 4S₂₅ ˜4S₂₈.

NS_(cn) is a general expression for said switches, wherein N denotes thestage number, c denotes a clock phase, and n denotes the switch number.

Hence, a fully-differential output voltage gain is: ##EQU4##

Using the clock signal which is manipulated in the above-mentionedmethod, a voltage gain can be obtained according to the following chart:

    __________________________________________________________________________    order                                                                            switch on the operation                                                                   a ratio of the capacitor                                                                       gain  dB!                                     __________________________________________________________________________    0  1(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                                    C.sub.1S /(C.sub.1H + C.sub.2H + C.sub.3H + C.sub.4H)                                          0                                                (1˜4)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           8C.sub.1H /8C.sub.1H                                           1  (1˜2)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S)/(C.sub.1H + C.sub.2H + C.sub.3H +                       C.sub.4H) =      +1.5                                             (1˜4)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           9.508C.sub.1H /8C.sub.1H                                       2  (1˜3) (S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                         (C.sub.1S + C.sub.2S + C.sub.3S)/(C.sub.1H + C.sub.2H +                       C.sub.3H +       +3.0                                             (1˜4)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           C.sub.4H) = 11.3C.sub.1H /8C.sub.1H                            3  (1˜4) (S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                         (C.sub.1S + C.sub.2S + C.sub.3S + C.sub.4S)/(C.sub.1H +                       C.sub.2H +       +4.5                                             (1˜4) (S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                          C.sub.3H + C.sub.4H) = 13.43C.sub.1H /8C.sub.1H                4  1(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                                    C.sub.1S /(C.sub.1H + C.sub.2H + C.sub.3H)                                                     +6.0                                             (1˜3)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           8C.sub.1H /4C.sub.1H                                           5  (1˜2)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S)/(C.sub.1H + C.sub.2H + C.sub.3H)                                         +7.5                                             (1˜3)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           9.508C.sub.1H /4C.sub.1H                                       6  (1˜3)(S.sub.11 ˜S.sub.14, S.sub.21˜S.sub.24),                           (C.sub.1S + C.sub.2S + C.sub.3S)/(C.sub.1H + C.sub.2H +                       C.sub.3H) =      +9.0                                             (1˜3)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           11.3C.sub.1H /4C.sub.1H                                        7  (1˜4)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S + C.sub.3S + C.sub.4S)/(C.sub.1H +                       C.sub.2H +       +10.5                                            (1˜3)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           C.sub.3H) = 13.43C.sub.1H /4C.sub.1H                           8  1(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                                    C.sub.1S /(C.sub.1H + C.sub.2H) =                                                              +12.0                                            (1˜2)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           8C.sub.1H /2C.sub.1H                                           9  (1˜2)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S)/(C.sub.1H + C.sub.2H)                                                    +13.5                                            (1˜2)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           9.508C.sub.1H /2C.sub.1H                                       10 (1˜3)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S + C.sub.3S)/(C.sub.1H + C.sub.2H)                                         +15.0                                            (1˜2)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           11.3C.sub.1H /2C.sub.1H                                        11 (1˜4)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S + C.sub.3S + C.sub.4S)/(C.sub.1H +                       C.sub.2H) =      +16.5                                            (1˜2)(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                           13.43C.sub.1H /2C.sub.1H                                       12 1(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                                    C.sub.1S /C.sub.1H = 8C.sub.1H /8 C.sub.1H                                                     +18.0                                            1(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                      13 (1˜2)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S)/C.sub.1H =                                                               +19.5                                            1(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                                     9.508C.sub.1H /C.sub.1H                                        14 (1˜3)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S + C.sub.3S)/C.sub.1H                                                      +21.0                                            1(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                                     11.3C.sub.1H /C.sub.1H                                         15 (1˜4)(S.sub.11 ˜S.sub.14, S.sub.21 ˜S.sub.24),                          (C.sub.1S + C.sub.2S + C.sub.3S + C.sub.4S)/C.sub.1H                                           +22.5                                            1(S.sub.15 ˜S.sub.18, S.sub.25 ˜S.sub.28)                                     13.43C.sub.1H /C.sub.1H                                        __________________________________________________________________________

As described above, the present invention makes it possible to generatea differential input signal, which is used as an input to an ADC of anaudio CODEC, by using a fully-differential output operational amplifierwhose output is transmitted as a differential output.

Also, the present invention gives an advantage of making a chip sizesmaller than the prior art does, resulting from the fact that resistorsare replaced by capacitors and switches while integrating.

What is claimed:
 1. A voltage gain amplifier for converting a singleinput to a differential output, comprising:a fully-differential outputoperational amplifying means, which has an inversion input terminal, anon-inversion input terminal, an inversion output terminal and anon-inversion output terminal, for amplifying two inputted signals andthen outputting the two amplified signals to the inversion outputterminal and the non-inversion output terminal, respectively, a phase ofthe one output signal being opposite to a phase of the other outputsignal; a first single input charging/discharging means connected tosaid inversion input terminal of said fully-differential outputoperational amplifying means, for charging/discharging an input voltageas a first signal; a second single input charging/discharging means forproviding a second signal whose phase is inversed compared with a phaseof the first signal provided by said first single inputcharging/discharging means, connected to said non-inversion inputterminal of said fully-differential output operational amplifying means;a first input voltage transferring means, of which one end is connectedto said inversion input terminal of said fully-differential outputoperational amplifying means and the other end is connected to saidinversion output terminal, for transferring the first signal by aswitching operation; a second input voltage transferring means, of whichone end is connected to said non-inversion input terminal of saidfully-differential output operational amplifying means and the other endis connected to said non-inversion output terminal, for transferring thesecond signal by a switching operation; and a frequency compensatingmeans for outputting the amplified first and second signals of saidfully-differential output operational amplifying means which can bestably operated within a given bandwidth.
 2. A voltage gain amplifierfor converting a single input to a differential output as claimed inclaim 1, further comprising a first and second voltage holding means,one end of the first voltage holding means being connected to saidinversion input terminal of said fully-differential output operationalamplifying means and the other end of the first voltage holding meansbeing connected to said inversion output terminal, one end of the secondholding means being connected to said non-inversion input terminal, theother end of the second holding means being connected to saidnon-inversion output terminal, for decreasing high-frequency noise.
 3. Avoltage gain amplifier for converting a single input to a differentialoutput as claimed in claim 2, wherein said first voltage holding meanscomprises a fifth capacitor connected between the inversion inputterminal and the inversion output terminal of said fully-differentialoutput operational amplifying means.
 4. A voltage gain amplifier forconverting a single input to a differential output as claimed in claim2, wherein said second voltage holding means comprises a sixth capacitorconnected between the non-inversion input terminal and the non-inversionoutput terminal of said fully-differential output operational amplifyingmeans.
 5. A voltage gain amplifier for converting a single input to adifferential output as claimed in claim 1, wherein said first singleinput charging/discharging means comprises:a first switch for switchingthe input voltage; a first sampling capacitor of which one end isconnected to said first switch; a second switch connected between theother end of said first sampling capacitor and an inversion inputterminal of said fully-differential output operational amplifying means;a third switch connected between one end of said first samplingcapacitor and the ground; and a fourth switch connected between theother end of said first sampling capacitor and the ground.
 6. A voltagegain amplifier for converting a single input to a differential output asclaimed in claim 5, wherein said second single inputcharging/discharging means comprises:a fifth switch for switching theinput voltage; a sixth switch connected between said fifth switch and anon-inversion input terminal of said fully-differential outputoperational amplifying means; a second sampling capacitor of which oneend being connected between said fifth switch and said sixth switch; anda seventh switch and an eighth switch connected in parallel between theother end of said second sampling capacitor and the ground.
 7. A voltagegain amplifier for converting a single input to a differential output asclaimed in claim 6, wherein said first input voltage transferring meanscomprises;a ninth switch connected to the inversion input terminal ofsaid fully-differential output operational amplifying means; a thirdcapacitor, one end of which connected to said ninth switch; a tenthswitch connected between the other end of said third capacitor and theinversion output terminal; and an eleventh switch and a twelfth switcheach connected between respective end of said third capacitor and theground.
 8. A voltage gain amplifier for converting a single input to adifferential output as claimed in claim 7, wherein the first switch, thefourth switch, the fifth switch, the eighth switch, the eleventh switchand the twelfth switch are operated by a clock signal whose phase isopposite to the phase of a clock signal which controls the secondswitch, the third switch, the sixth switch, the seventh switch, theninth switch and the tenth switch.
 9. A voltage gain amplifier forconverting a single input to a differential output as claimed in claim6, wherein said second input voltage transferring means comprises;athirteenth switch connected to the non-inversion input terminal of saidfully-differential output operational amplifying means; a fourthcapacitor, one end of which connected to said thirteenth switch; afourteenth switch connected between the other end of said fourthcapacitor and the non-inversion output terminal; and a fifteenth switchand a sixteenth switch each connected between respective end of saidfourth capacitor and the ground.
 10. A voltage gain amplifier forconverting a single input to a differential output as claimed in claim9, wherein the first switch, the fourth switch, the fifth switch, theeighth switch, the fifteenth switch and the sixteenth switch areoperated by a clock signal whose phase is opposite to the phase of aclock signal which controls the second switch, the third switch, thesixth switch, the seventh switch, the thirteenth switch and thefourteenth switch.
 11. A voltage gain amplifier for converting a singleinput to a differential output as claimed in claim 1, wherein saidfrequency compensating means comprises:a seventh capacitor connectedbetween the inversion output terminal and the ground; and an eighthcapacitor connected between the non-inversion output terminal and theground.
 12. A voltage gain amplifier for converting a single input to adifferential output as claimed in claim 1, wherein said first and secondsingle input charging/discharging means are composed of a plurality ofcharging/discharging parts connected in parallel, respectively, and saidfirst and second input voltage transferring means also have a pluralityof input voltage transferring means whose inter-connection is parallel,respectively.
 13. A voltage gain amplifier for converting a single inputto a differential output as claimed in claim 12, wherein said first andsecond single input charging/discharging means and said first and secondinput voltage transferring means have a 4-stage parallel connection,capacitors have the following relations:the capacitance of a first-stagecapacitor of said first and second input voltage transferring means isthe same as the capacitance of a second-stage capacitor of said firstand second input voltage transferring means; the capacitance of athird-stage capacitor of said first and second input voltagetransferring means is two times the capacitance of the first-stagecapacitor of said first and second input voltage transferring means; thecapacitance of a fourth-stage capacitor of said first and second inputvoltage transferring means is four times the capacitance of thefirst-stage capacitor of said first and second input voltagetransferring means; the capacitance of a first-stage capacitor of saidfirst and second single input charging/discharging means is eight timesthe capacitance of the first-stage capacitor of said first and secondinput voltage transferring means; the capacitance of a second-stagecapacitor of said first and second single input charging/dischargingmeans is 0.1885 times the capacitance of the first-stage capacitor ofsaid first and second single input charging/discharging means; thecapacitance of a third-stage capacitor of said first and second singleinput charging/discharging means is 0.22404 times the capacitance of thefirst-stage capacitor of said first and second single inputcharging/discharging means; and the capacitance of a fourth-stagecapacitor of said first and second single input charging/dischargingmeans is 0.26626 times the capacitance of the first-stage capacitor ofsaid first and second single input charging/discharging means.